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University of Southern Mississippi

Undergraduate Research Assistant · Aug 2024 – present · Hattiesburg, MS

Design authentication hardware: FPGA key schemes in VHDL-2019 for eVTOL drones, and a privacy-preserving noise layer for smart-grid meters, each taken from scheme to synthesized hardware.

What I did

  • Generated 800 authentication keys in 1.68 ms within 25 KB of memory overhead by implementing Chebyshev chaotic-map key streaming in VHDL-2019 and synthesizing it in AMD Vivado, so an eVTOL fleet stores no key material on the aircraft.
  • Held authentication latency at 10 ms on 20.9% LUT and 8.7% flip-flop utilization by optimizing the RTL against the Vivado timing and utilization reports.
  • Sustained 25 MSamples/s of privacy-preserving aggregation at 200 mW and 9.70% LUT on a Nexys A7-100T by writing the noise layer in RTL as a pipelined multiply-accumulate datapath mapped onto the FPGA’s DSP slices. The first-author paper was accepted at the 4th International Conference on AI, Blockchain and IoT (2026).

What it produced

research

Smart-Meter Aggregation

Meters are paired so their added noise cancels exactly at the aggregator: the utility reads a true sum while no individual reading is recoverable from the stream. The noise layer is written in RTL and runs on a Nexys A7-100T at 100 MHz as a pipelined multiply-accumulate datapath mapped onto the FPGA’s DSP slices, which is the structure a filter or a correlator is built from.

research

Chaotic-Map Key Streaming

An FPGA authentication scheme for eVTOL drones built on Chebyshev chaotic maps and SHA in VHDL-2019. Keys are generated from a shared seed on demand rather than stored, so a fleet’s key material never sits on the aircraft.

research

Dynamic Wireless Charging

A framework for charging a vehicle while it is still moving. Every expensive operation moves off the real-time path into offline registration, so authentication finishes inside the milliseconds an electric vehicle spends over a charging pad at highway speed. Per-session pseudonyms keep the route private, and settlement is decentralized so no single provider holds the account. Written under the CRA UR2PhD program, where the proposal was presented and the program certification completed.

VHDL · RTL design · AMD Vivado · FPGA · DSP · IEEE